november 2009 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN424C / fin425c ? rev. 1.0.0 serdes? FIN424C / fin425c ? 20-bit ultra-low-power serializer / deserializer for controller and rgb displays FIN424C / fin425c 20-bit ultra-low-power serializer / deserializer for controller and rgb displays features data & control bits 20 frequency 10mhz capability qvga interface microcontroller / rgb controller usage i86 & m68 selectable edge rates yes dynamic current 9ma / pair standby current 10a core voltage (v dda/s ) 2.5 to 3.0v i/o voltage (v ddp ) 1.6v to v dda/s esd 15kv (iec) package mlp-32 (5 x 5mm) ordering information FIN424Cmlx fin425cmlx applications ? slider, folder, and clamshell mobile handsets ? gsm and cdma phones description the FIN424C and fin425c serdes? are a low-power serializer/ deserializer pair that can help minimize the cost and power of an lcd interface. they are designed to operate transparently between the baseband processor and lcd. /we and chip-select timing is maintained from the serializer to the deserializer. through the use of serialization, the number of signals transferred from one point to another can be significantly reduced. typical reduction is 5:1. through the use of differential signaling, shielding, and emi filters can also be minimized, further reducing the cost of serialization. differential signaling is important for providing a noise-insensitive signal that can withstand radio and electrical noise sources. major reduction in power consumption allows minimal impact on battery life in mobile applications. related resources for more information, please visit: http://www.fairchildsemi.com/products/interface/userdes.html typical application deserializer 20-bit deserializer + - + - serializer 20-bit serializer baseband + - + - 2 2 70-130 ohms built-in voltage translation main display simple interface internal termination deserializer 20-bit deserializer + - + - serializer 20-bit serializer baseband + - + - 2 2 70-130 ohms built-in voltage translation main display simple interface internal termination figure 1. mobile phone example
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN424C / fin425c ? rev. 1.0.0 2 serdes? FIN424C / fin425c ? 20-bit ultra-low-power serializer / deserializer for controller and rgb displays FIN424C serializer pin descriptions pin name description strb lvcmos st robe signal for latching data into the serializer (on rising edge) dp[19:0] lvcmos data input /res low-power mode 0 serializer low power 1 serializer enabled /stby serdes standby 0 serializer and deserializer in low power 1 serializer and deserializer enabled test internal use (should be gnd) ds+, ds- serial data output cks+, cks- serial clock output vddp power supply for parallel i/o and internal circuitry vdds power supply for serial i/o vdda power supply for core gnd ground pins notes: 1. 0 = v il ; 1 = v ih . 2. all gnd and vddp pins must be connected to ground and vddp, respectively. 11 12 13 14 15 31 30 28 27 26 25 gnd pad must be grounded cks+ dp[12] dp[11] dp[10] vddp dp[9] dp[8] dp[7] dp[6] dp[19] dp[18] dp[17] dp[16] dp[15] strb dp[14] dp[13] dp[0] dp[1] dp[2] dp[3] dp[4] dp[5] 1 cks- 2 4 vdds vdda 3 ds- 5 ds+ 6 /res 7 vddp 8 10 test 9 /stby 32 20 21 19 23 18 16 17 22 24 29 11 12 13 14 15 31 30 28 27 26 25 gnd pad must be grounded cks+ dp[12] dp[11] dp[10] vddp dp[9] dp[8] dp[7] dp[6] dp[19] dp[18] dp[17] dp[16] dp[15] strb dp[14] dp[13] dp[0] dp[1] dp[2] dp[3] dp[4] dp[5] 1 cks- 2 4 vdds vdda 3 ds- 5 ds+ 6 /res 7 vddp 8 10 test 9 /stby 32 20 21 19 23 18 16 17 22 24 29 figure 2. FIN424Cmlx mlp-32 pinout (top through view)
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN424C / fin425c ? rev. 1.0.0 3 serdes? FIN424C / fin425c ? 20-bit ultra-low-power serializer / deserializer for controller and rgb displays fin425c deserializer pin descriptions pin name description wclk lvcmos strb output dp[19:0] lvcmos data output /res low-power mode 0 deserializer low power 1 deserializer enabled slew parallel output edge rate control 0 slow output edge rates 1 fast output edge rates test internal use (should be gnd) ds+, ds- serial data input cks+, cks- serial clock input vddp power supply for parallel i/o and internal circuitry vdds power supply for serial i/o vdda power supply for core gnd ground pins notes: 3. 0 = v il ; 1 = v ih . 4. all gnd and vddp pins must be connected to ground and vddp, respectively. 11 12 13 14 15 31 30 28 27 26 25 gnd pad must be grounded cks+ dp[12] dp[11] dp[10] vddp dp[9] dp[8] dp[7] dp[6] dp[19] dp[18] dp[17] dp[16] dp[15] wclk dp[14] dp[13] dp[0] dp[1] dp[2] dp[3] dp[4] dp[5] 1 cks- 2 4 v dds v dda 3 ds- 5 ds+ 6 /res 7 v ddp 8 10 test 9 slew 32 20 21 19 23 18 16 17 22 24 29 11 12 13 14 15 31 30 28 27 26 25 gnd pad must be grounded cks+ dp[12] dp[11] dp[10] vddp dp[9] dp[8] dp[7] dp[6] dp[19] dp[18] dp[17] dp[16] dp[15] wclk dp[14] dp[13] dp[0] dp[1] dp[2] dp[3] dp[4] dp[5] 1 cks- 2 4 v dds v dda 3 ds- 5 ds+ 6 /res 7 v ddp 8 10 9 slew 32 20 21 19 23 18 16 17 22 24 29 figure 3. fin425cmlx mlp-32 pinout (top through view)
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN424C / fin425c ? rev. 1.0.0 4 serdes? FIN424C / fin425c ? 20-bit ultra-low-power serializer / deserializer for controller and rgb displays table 1. reset and standby modes / states /res FIN424C fin425c /stby FIN424C mode pins FIN424C parallel input state fin425c parallel output state 0 x reset mode dp[19:0] disabled low strb / wclk disabled high 1 0 standby mode dp[19:0] disabled last state strb / wclk disabled high 1 1 operating mode dp[19:0] enabled enabled strb / wclk enabled enabled application diagram strb dp[15:0] dp[16] dp[17] dp[18] dp[19] /res /stby test cks+ cks- ds+ ds- vddp vdds/a /we dp[15:0] a0 cs1 cs2 reset /stby baseband processor gnd cks+ cks- ds+ ds- gnd main display 16-bit controller /we a0 data[15:0] reset /cs vddp vdds/a FIN424C fin425c 1.8v 2.8v wclk dp[15:0] dp[16] dp[17] dp[18] dp[19] slew test /res sub-display 8-bit controller /we a0 data[7:0] reset /cs 2.8v 2.8v - - - - - /we a0 data[15:0] reset /cs - 8 figure 4. dual-display, 16-bit, controller interface
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN424C / fin425c ? rev. 1.0.0 5 serdes? FIN424C / fin425c ? 20-bit ultra-low-power serializer / deserializer for controller and rgb displays strb dp[17:0] dp[18] dp[19] /res /stby test cks+ cks- ds+ ds- vddp vdds/a /we dp[17:0] a0 cs reset /stby baseband processor gnd cks+ cks- ds+ ds- gnd main display 18-bit controller /we data[17:0] /a0 cs reset vddp vdds/a FIN424C fin425c 1.8v 2.8v wclk dp[17:0] dp[18] dp[19] slew test /res 2.8v 2.8v - - - - - figure 5. single?display, 18-bit, controller interface strb dp[17:0] dp[18] dp[19] /res /stby test cks+ cks- ds+ ds- vddp vdds/a pclk dp[17:0] hsync vsync /cs reset /stby baseband processor gnd cks+ cks- ds+ ds- gnd main display 18-bit rgb pclk data[17:0] hsync vsync /cs reset vddp vdds/a FIN424C fin425c 1.8v 2.8v wclk dp[17:0] dp[18] dp[19] slew test /res 2.8v 2.8v - - - - - figure 6. single-display, 18-bit, rgb interface additional application information flex cabling: the serial i/o information is transmitted at a high serial rate. care must be taken implementing this serial i/o flex cable. the following best practices should be us ed when developing the flex cabling or flex pcb. ? keep all four differential serial wires the same length. ? do not allow noisy signals over or near differential serial wires. example: no cmos traces over differential serial wires. ? use a design goal of 70 to 130 differential characteristic impedance. ? do not place test points on differential serial wires. ? design differential serial wires a minimum of 2cm away from the antenna. ? visit fairchild?s website at http://www.fairchildsemi.com/pr oducts/interface/userdes.html , contact your sales representative, or contact fairchild directly at interface@fairchildsemi.com for applications notes or flex guidelines.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN424C / fin425c ? rev. 1.0.0 6 serdes? FIN424C / fin425c ? 20-bit ultra-low-power serializer / deserializer for controller and rgb displays absolute maximum ratings stresses exceeding the absolute maximum ratings may damage t he device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating c onditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd supply voltage -0.5 +3.6 v v io all input / output voltage -0.5 v ddp +0.5 v t stg storage temperature range -65 +150 c t j maximum junction temperature +150 c t l lead temperature (soldering, four seconds) +260 c esd iec 61000 board level 15.0 kv human body model, jesd22-a114 all pins 7.5 serial i/o, /res, par/spi to gnd 14.0 recommended operating conditions the recommended operating conditions table defines the condi tions for actual device operation. recommended operating conditions are specified to ensure optim al performance to the datasheet specific ations. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dda , v dds (5) supply voltage 2.5 3.0 v v ddp supply voltage 1.6 v dda/s v t a operating temperature -30 +85 c notes : 5. v dda and v dds supplies must be hardwired together to the same power supply. v ddp must be less than or equal to v dda /v dds . 6. typical values are tested at t a =25c and 2.75v.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN424C / fin425c ? rev. 1.0.0 7 serdes? FIN424C / fin425c ? 20-bit ultra-low-power serializer / deserializer for controller and rgb displays electrical specifications values valid for over-supply voltage and operating te mperature ranges unless otherwise specified. symbol parameter test conditions min. typ. max. unit dc parallel i/o and serial characteristics v ih input high voltage 0.7 x v ddp v ddp v v il input low voltage gnd 0.3 x v ddp v v oh output high voltage slew=0 i oh =-250a 0.8 x v ddp v slew=1 i oh =-1ma v ol output low voltage slew=0 i ol =250a 0.2 x v ddp v slew=1 i ol =1ma i in input current -5 5 a v go serial input voltage ground offset fin425c to FIN424C 0 v z serial transmission line impedance 70 100 130 power characteristics i dyn_FIN424C dynamic current FIN424C v dda/s =2.75v, v ddp =1.8v, /stby=1, /res=1 5.44mhz 4 ma i dyn_fin425c dynamic current fin425c v dda/s =2.75v v ddp =1.8v, /stby=1, /res=1, c l =0pf 5.44mhz 5 ma i brst_FIN424C burst standby current FIN424C v dda/s =2.75v, v ddp =1.8v, /stby=1, /rst=1, no strobe signal, 1.3 ma i brst_fin425c burst standby current fin425c v dda/s =2.75v, v ddp =1.8v, /stby=1, /rst=1, no strobe signal, c l =0pf 1.8 ma i stby standby current FIN424C / fin425c v dds/a =v ddp =3.0v, /stby=0, /rst=1 10 a i res reset current FIN424C / fin425c v dds/a =v ddp =3.0v, /rst=0 10 a ac FIN424C specifications f wstrb0 strobe frequency 0 10 mhz t r , t f input edge rates 40 ns t s1 dp setup time dp before strbn (7) 5 ns t h1 dp hold time dp after strbn (7) 15 ns ac fin425c specifications t r0 , t f0 output edge rates of wclk slew=0, cl=5pf 20% to 80% (7) 8 17 ns slew=1, c l =5pf 20% to 80% (7) 10 t r1 , t f1 output edge rates of dp[19:0] slew=0, c l =5pf 20% to 80% (7) 8 22 ns slew=1, c l =5pf 20% to 80% (7) 17 tcs dp[19:0] to falling edge of wclk c l =5pf 20% to 80% t pwl t cs dp wclk t pwl t cs dp wclk 0 4 t pwl wclk output pulse width low, measured 30% to 30% (7) 50 56 ns ac oscillator specifications f osc serial operating frequency 240 275 310 mhz t osc-stby oscillator stabilization time after standby v dda =v dds =2.75v /res=1, /stby transition 15 30 s
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN424C / fin425c ? rev. 1.0.0 8 serdes? FIN424C / fin425c ? 20-bit ultra-low-power serializer / deserializer for controller and rgb displays symbol parameter test conditions min. typ. max. unit t osc-res oscillator stabilization time after reset v dda =v dds =2.75v /stby=1, /res transition 30 50 s ac reset and standby timing t strb-res /res after last strbn t strb-res strb /stby /res t strb- stby t strb-res strb /stby /res t strb- stby 0 ns t strb-stby standby time after last strobe 200 ns t vdd-skew allowed power up skew between v ddp and v dda/s t vdd-skew strb /stby /res vddp vdda/s t vdd-res t res-stby t osc-stby t vdd-skew strb /stby /res vddp vdda/s t vdd-res t res-stby t osc-stby - + ms t vdd-res minimum reset low time after v dd stable 20 s t res-stby /stby wait time after /res 20 s note : 7. characterized, but not production tested.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN424C / fin425c ? rev. 1.0.0 9 serdes? FIN424C / fin425c ? 20-bit ultra-low-power serializer / deserializer for controller and rgb displays physical dimensions 5.00 5.00 0.80 max 0.10 c seating plane 0.08 c 0.05 0.00 (0.20) c 0.15 c 0.15 c pin #1 ident 0.50 pin #1 ident 3.70 3.50 0.45 0.35 3.70 3.50 0.50 0.10 cab 0.05 c 0.18-0.30 a b 5.38 min 0.20min 3.86 min 3.37 max 0.28 max 0.50typ (0.76) x4 x40 e (datum b) (datum a) pin #1 id pin #1 id (0.25 ) notes: a. conforms to jedec registration mo-220, variation whhd-4. this package is also footprint compatible with whhd-5. b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m-1994. d. land pattern per ipc sm-782. e. width reduced to avoid solder bridging. f. dimensions are not inclusive of burrs, mold flash, or tie bar protrusions. g. drawing filename: mkt-mlp32arev3. figure 7. 32-lead, molded leadless package (mlp), qu ad, jedec mo-220, variation whhd-4, 5mm square package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner wit hout notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to verify or o btain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specificall y the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . ordering information part number operating temperature range eco status package packing method FIN424Cmlx -30 to +85c green 32-lead, molded leadless package (mlp), quad, jedec mo-220, variation whhd-4, 5mm square tape and reel fin425cmlx -30 to +85c green 32-lead, molded leadless package (mlp), quad, jedec mo-220, variation whhd-4, 5mm square tape and reel for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com FIN424C / fin425c ? rev. 1.0.0 10 serdes? FIN424C / fin425c ? 20-bit ultra-low-power serializer / deserializer for controller and rgb displays
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